1. Field of the Invention
The present invention relates to a semiconductor device including a rail-to-rail amplifier circuit.
2. Description of the Related Art
FIG. 1 conceptually shows a method of using digital-to-analog converter (DAC) circuits 200 and rail-to-rail operational amplifiers 300 to drive a load (for example, pixels of a liquid crystal display panel) in a subsequent stage. If it is preferable for the operational amplifiers 300 to amplify and output signals supplied from the DAC circuits 200 to signals of maximum amplitude in a supply voltage range from high voltage to low voltage, the adoption of rail-to-rail amplifiers capable of maximizing the output amplitude to approximate the supply voltage range is effective.
The rail-to-rail amplifiers 300, which include a differential input Nin including an n-channel transistor pair and a differential input Pin including a p-channel transistor pair, select the operation of the differential input Pin and the differential input Nin in accordance with the voltage of an input signal, and output an amplified signal with an amplitude of the entire voltage range from high-voltage supply Vcc to low-voltage supply Vss of the amplifier with respect to the input voltage. This type of rail-to-rail amplifier is disclosed in Japanese Patent Laid-Open Publication 2005-124173 and so forth.
FIG. 2 shows one example of a circuit configuration of the rail-to-rail operational amplifier of the related art. An operational amplifier has a positive input terminal IN1 and an inverting input terminal IN2 at a differential input section and further a differential input Nin configured from a differential pair of n-channel transistors Qn1 and Qn2 and a differential input Pin configured from a differential pair of p-channel transistors Qp1 and Qp2, where the differential inputs Nin and Pin are respectively connected to the transistors corresponding to both terminals IN1 and IN2.
Between the differential input Pin and the high-voltage supply Vcc are provided an always-on p-channel transistor (hereinafter referred to as a current supply transistor) Qp24, which functions as a current supply, and p-channel transistors Qp25 and Qp26 forming a current mirror circuit CMp1. A gate electrode of the current supply transistor Qp24 is connected to a bias supply Vbp2 and the current supply transistor Qp24 supplies a constant current from the supply Vcc to a terminal connected in common with the differential input Pin in accordance with the bias supply voltage Vbp2.
A source electrode of the current input side transistor Qp26 of the current mirror circuit CMp1 is connected to the supply Vcc and gate and drain electrodes are connected to each other and connected to a drain electrode of an n-channel transistor Qn23.
A source electrode of the n-channel transistor Qn23 is connected to a common terminal of the differential input Nin and a drain electrode of an always-on current supply transistor Qn24 while a gate electrode is connected to a bias supply Vbn1.
Between the differential input Nin and the low-voltage supply Vss are provided the always-on n-channel transistor (hereinafter referred to as a current supply transistor) Qn24, which functions as a current supply, and n-channel transistors Qn25 and Qn26 forming a current mirror circuit CMn1. A gate electrode of the current supply transistor Qn24 is connected to a bias supply Vbn2 and the current supply transistor Qn24 draws a constant current from the terminal connected in common with the differential input Nin to the supply Vss in accordance with the bias supply voltage Vbn2.
Furthermore, the current input side transistor Qn26 of the current mirror circuit CMn1 has a source electrode connected to the supply Vss and gate and drain electrodes connected to each other and connected to a drain electrode of a p-channel transistor Qp23. A source electrode of the p-channel transistor Qp23 is connected to a common terminal of the differential input Pin and a drain electrode of the current supply transistor Qp24, and a gate electrode of the transistor Qp23 is connected to a bias supply Vbp1.
The rail-to-rail amplifier 300 that includes the differential input section, current supply, and current mirror circuit further includes a buffer section and an output section. The buffer section includes transistors Qp31 to Qp37 and Qn31 to Qn37. The output section includes a p-channel output transistor Qop1, which is provided between the high voltage side supply Vcc and an output terminal Out, and an n-channel output transistor Qon1, which is provided between the low voltage side supply Vss and the output terminal Out. At the buffer section, the current of a differential signal is adjusted in accordance with signals input by the differential inputs Pin and Nin, and an amplified signal is output from the output terminal Out in accordance with the difference in voltages applied to the positive input terminal IN1 and the inverting input terminal IN2. Negative feedback is provided for the amplifier 300 by connecting the inverting input terminal IN2 with the output terminal Out.
In a voltage range where the voltage of an analog signal supplied to the positive input terminal IN1 from the DAC 200 is lower than a voltage Vpcom−|Vthp|, which is the common terminal voltage (VPcom) of the differential input Pin minus a threshold voltage (|Vthp|) of the transistor Qp1, and lower than a voltage VNcom+|Vthn|, which is the voltage at the common terminal (VNcom) of the differential input Nin to which is added a threshold voltage (|Vthn|) of the transistor Qn1, only the differential input Pin operates. Generally, in the voltage range where only the differential input Pin operates, the n-channel transistor Qn23 is set to turn on, a current flows to the transistor Qp26 of the current mirror circuit CMp1 in accordance with the amount of current drawn by the current supply transistor Qn24 toward the low voltage side supply Vss, and a corresponding current is supplied via the transistor Qp25 to a terminal in common with the transistor pair at the differential input Pin.
In a voltage range where the voltage of the analog signal supplied to the positive input terminal IN1 is higher than the common input terminal of the differential input Nin by the amount of the threshold voltage of the transistor Qn1 and where the above-mentioned differential input Pin is operational, both differential inputs Pin and Nin operate. As the above-mentioned differential input Nin operates, the voltage of the common terminal rises, and when it becomes higher than the bias voltage Vbn1 by the amount of the operating threshold voltage of the transistor Qp23, the transistor Qn23 turns off and the current mirror circuit CMp1 does not operate. Furthermore, since the difference between the voltage of the common terminal of the differential input Pin during operation and the bias voltage Vbp1 is set so as to be smaller than the operating threshold voltage of the transistor Qp23, the p-channel transistor Qp23 turns off and the current mirror circuit CMn1 does not operate.
When the voltage of the analog signal supplied to the positive input terminal IN1 becomes higher than the voltage (Vpcom−|Vthp|) at which the differential input Pin is operational, the differential input Pin does not operate, and when it is higher than the voltage (Vncom+|Vthn|) at which the differential input Nin is operational, only the differential input Nin operates. In this case, the voltage of the common input terminal of the differential input Pin, to which is connected the source electrode of the p-channel transistor Qp23, is high, the p-channel transistor Qp23 turns on, the current mirror circuit CMn1 operates, a current flows via the transistor Qp23 to the transistor Qn26 of the current mirror circuit CMn1 in accordance with the amount of current flowing from the high voltage side supply Vcc through the current supply transistor Qp24, and a corresponding current is drawn via the transistor Qn25 from the terminal in common with the transistor pair at the differential input Nin.
The above-mentioned amplifier 300 operates as a rail-to-rail amplifier and can yield an output voltage substantially covering the supply voltage range (Vss to Vcc). However, as described hereinabove, the current mirror circuits CMp1 and CMn1 are included in addition to the current supply transistors Qp24 and Qn24 so that the total currents respectively flowing through the two differential inputs Pin and Nin are equal both in the voltage range where only the differential input Pin operates or where only the differential input Nin operates and in the voltage range where both differential inputs Pin and Nin operate. The current mirror circuits CMp1 and CMn1 are current elements and require a large substrate area to be included into an integrated circuit. Furthermore, at an input voltage range on the low voltage side where only the differential input Pin operates, power dissipation due to the current flowing through the current mirror circuit CMp1 cannot be avoided, and at an input voltage range on the high voltage side where only the differential input Nin operates, power dissipation due to the current flowing through the current mirror circuit CMn1 cannot be avoided.
Accordingly, a method can be devised in which are provided two so-called single-channel input amplifiers having only p-channel or n-channel differential inputs, and in which these two amplifiers are selected in accordance with an input voltage. However, if two amplifiers having opposite polarities are used, the differential linearity error at the switching part for the two amplifiers becomes large. In particular, the switching part for the two amplifiers is in the vicinity of the center of the voltage amplitude of the input analog signal and although the probability of the analog signal existing in such a range is generally high, an increase in error in this region is not desirable. Furthermore, since two amplifiers are required, the number of elements increases two times, which is disadvantageous in terms of minimizing the surface area of the overall device, which includes the amplifiers.